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[其他] [AMD]上海logic design team内部推荐

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发表于 2012-5-7 21:30 |显示全部楼层
大家好,我是AMD上海研发中心logic design team的工程师。我们部门现在对外开放2个招聘名额,有兴趣的童鞋请把简历发至joe.li@amd.com
在这里,你能接触到graphic core里面最核心的设计。
以下是JD:
Design Engineer (MTS)
Responsibility:
• Develop micro-architecture for GPU blocks based on architectural requirement.
• Develop RTL code for GPU blocks in Verilog HDL and make sure functionalcorrect and reusable for different configuration.
• Synthesis and deliver netlist that meeting timing, area and powerrequirement. Help PD on the floorplanning and close timing.

Requirement:
• MS degree of EE with 5+ years working experience in ASIC Company.
• Expert of Verilog RTL design and has experience of large digital ASICproject.
• Familiar with front-end EDA tools and flows.
• Familiar with C/C++ programming and unix/linux and scripts (tcl, perl etc.)
• Fluent English on talking, presentation and writing documents.
• Work is performed with limited supervision. Strong sense of task schedulingand deliver on time as predetermined milestones committed to manager.
• Can solves complex, novel and non-recurring problems; initiates significantchanges to existing processes/methods and leads development and implementation
• Possesses specialized knowledge of Computer architecture and computerarithmetic (a plus)
• Possesses specialized knowledge of Computer graphic knowledge (a plus)
Design Engineer (Sr. Eng)
Responsibility:
• Develop micro-architecture for GPU blocks based on architectural requirement.
• Develop RTL code for GPU blocks in Verilog HDL and make sure functional correctand reusable for different configuration.
• Synthesis and deliver netlist that meeting timing, area and powerrequirement. Help PD on the floorplanning and close timing.

Requirement:
• MS degree of EE with 3+ years working experience in ASIC Company.
• Familiar with Verilog RTL design and has experience of digital ASIC project.
• Familiar with front-end EDA tools and flows.
• Familiar with C/C++ programming and unix/linux and scripts (tcl, perl etc.)
• Fluent English on talking, presentation and writing documents.
• Work is performed with limited supervision. Strong sense of task schedulingand deliver on time as predetermined milestones committed to manager.
• Possesses specialized knowledge of Computer architecture and computerarithmetic (a plus)

Design Engineer (NCG -> Eng2)
Responsibility:
·        Develop micro-architecturespecification for GPU blocks.
·        Develop RTL code for GPU blocksin Verilog HDL.
·        Responsible for Front-End chipimplementation including design, implementation and execution of the flow thatstarts with RTL code and ends with the delivery of a netlist package ready forphysical design.
·        Responsible for ASIC designmethodology and flow development, interfacing with EDA vendors on technology.
Requirement:
·        Master or above degree.
·        Major in Micro-E or related,Electronic Engineer, Computer Science, Mathematics. Communication.
·        Familiar with Verilog HDLcoding and ASIC Frond-End implementation flow.
·        Familiar with unix/linux andscripts (tcl, perl, python etc.).
·        Strong task-based organizationskills.
·        Computer architecture andcomputer arithmetic (a plus).
·        Computer graphic basicknowledge (a plus).
·        Experience with Databasetechnologies and database-driven custom web application development (a plus).
·        Proficient English and Mandarin(listening, writing and speaking).
·        Have project experience duringuniversity education.
·        Strong passion in achievementand career development.
·        A self-motivated team player.


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zeng32      

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发表于 2012-7-29 10:58 |显示全部楼层
唉,那种地方只能膜拜了
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发表于 2012-9-4 19:24 |显示全部楼层
请问一下楼主,您是否知道AMD今年校招是什么时候开始呢?是否有analog ic design的职位对应届生开放?
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