2008.10.11 nvidia vlsi physical design engineer 笔试回忆

CHEMMY

想起多少是多少吧 欢迎补充 一起攒rp

 

1，2 input NAND NOR gate schematic and true table。

2，Prime Timing  output file . CLOCK skew， hold setup time 。。。

3，critical path of a given circuit and setup time requirment

4，how to reduce leakage current

5，power consumption  formulation  of digital circuit

6，C shell/perl programming

7, antena effect of ic processing

8，given delay of 100um metal line ，caculate 1000um delay with and without buffers

9  " divide by 2 " circuit using D flip flops

 

 

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